Datasheet

Rev. 3.00 Sep. 28, 2009 Page xiv of xliv
REJ09B0350-0300
Item Page Revision (See Manual for Details)
15.6.5 Simultaneous Serial Data
Transmission and Reception
(Clocked Synchronous Mode)
Figure 15.20 Sample Flowchart
of Simultaneous Serial
Transmission and Reception
447 Figure amended
[5]
[6]
No
Yes
All data received?
Clear TE and RE bits in SCR to 0
End transmission/reception
16.3.8 FIFO Control Register
(FFCR)
476 Table amended
Bit Bit Name R/W Description
2 XMITFRST R/W0 Transmit FIFO Reset
The transmit FIFO data is cleared when 1 is written.
However, FTSR data is not cleared. This bit is
automatically cleared.
Initial Value
1 RCVRFRST R/W0 Receive FIFO Reset
The receive FIFO data is cleared when 1 is written.
However, FRSR data is not cleared.
This bit is automatically cleared.
16.4.4 Data Transmission/
Reception with Flow Control
Figure 16.6 Example of
Initialization Flowchart
493 Figure amended
[5] Select parity with the EPS and PEN bits in FLCR, and
set the stop bit with the STOP bit in FLCR. Then, set
the data length with the CLS1 and CLS0 bits in FLCR.
[6] Set the FIFOE bit in FFCR to 1 to enable the FIFO.
Set the receive FIFO trigger level with the RCVRTRIG1
and RCVRTRIG0 bits in FFCR. Select the best trigger
level to prevent an overflow of the receive FIFO.
Figure 16.10 Example of Data
Reception Flowchart
497 Figure amended
Read FLSR
Receive data ready interrupt
Read receive FIFO
Read FLSR
Error processing
(Transmission/reception standby flow)
BI = 1, FE = 1,
PE = 1, or OE = 1
DR = 0
No
Yes
[2]
[1]
[3]
[4]
[1] When data is received, a receive data ready
interrupt occurs. Go to the data reception flow
by using this interrupt trigger.
[2] Confirm that the BI, FE, PE, and OE flags in
FLSR are all cleared. If any one of these flags
is set to 1, perform error processing.
[3] Read the receive FIFO.
[4] Check the DR flag in FLSR. When the DR flag
is cleared and all of the data has been read, data
reception is complete.
16.6.2 FLCR Access During
Serial Transmission and
Reception
502 Newly added