Datasheet

Rev. 3.00 Sep. 28, 2009 Page xiii of xliv
REJ09B0350-0300
Item Page Revision (See Manual for Details)
15.5.1 Multiprocessor Serial Data
Transmission
Figure 15.11 Sample
Multiprocessor Serial
Transmission Flowchart
436 Figure amended
No
Yes
[4]
[5]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
Break output?
End transmission
15.5.2 Multiprocessor Serial Data
Reception
Figure 15.13 Sample
Multiprocessor Serial Reception
Flowchart (1)
438 Figure amended
Clear RE bit in SCR to 0
Error processing
(Continued on next page)
[5]
No
Yes
All data received?
[6]
End reception
15.6.3 Serial Data Transmission
(Clocked Synchronous Mode)
Figure 15.17 Sample Serial
Transmission Flowchart
443 Figure amended
No
Yes
Clear TE bit in SCR to 0
TEND = 1
[4]
End transmission
15.6.4 Serial Data Reception
(Clocked Synchronous Mode)
Figure 15.19 Sample Serial
Reception Flowchart
445 Figure amended
<End>
[6]
Clear RE bit in SCR to 0
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
[3]
End reception