Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 98 of 910
REJ09B0350-0300
• ISR
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
• When writing 0 to IRQnF flag after reading
IRQnF = 1
• When interrupt exception handling is executed
when low-level detection is set and IRQn or
ExIRQn input is high
• When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 7 to 0)
Note: The IRQn or ExIRQn pin is selected by the
IRQ sense port select register (ISSR). The
ExIRQ5 to ExIRQ0 pins are not supported.
Note: * Only 0 can be written for clearing the flag.