Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 97 of 910
REJ09B0350-0300
5.3.6 IRQ Status Registers (ISR16, ISR)
The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
• ISR16
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
[Setting condition]
When the interrupt source selected by the ISCR16
registers occurs
[Clearing conditions]
• When writing 0 to IRQnF flag after reading
IRQnF = 1
• When interrupt exception handling is executed
when low-level detection is set and IRQn or
ExIRQn input is high
• When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 15 to 8)
Note: The IRQn or ExIRQn pin is selected by the
IRQ sense port select register 16 (ISSR16).
Note: * Only 0 can be written for clearing the flag.