Datasheet

Rev. 3.00 Sep. 28, 2009 Page xii of xliv
REJ09B0350-0300
Item Page Revision (See Manual for Details)
15.1 Features
Figure 15.1 Block Diagram of
SCI
402 Figure amended
RxD
TxD
SCK
Clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
SCMR
SSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
BRR
Module data bus
RDR
TSRRSR
Parity generation
Parity check
TDR
Bus interface
Internal data bus
External clock
15.3 Register Descriptions
Table 15.2 Register
Configuration
404 Table amended
Channel Register Name
Channel 1
Channel 2
Serial mode register_1
Bit rate register_1
Serial control register_1
Transmit data register_1
Serial status register_1
Receive data register_1
Smart card mode register_1
Serial mode register_2
Bit rate register_2
Serial control register_2
Transmit data register_2
Serial status register_2
Receive data register_2
Smart card mode register_2
15.4.6 Serial Data Reception
(Asynchronous Mode)
Figure 15.9 Sample Serial
Reception Flowchart (1)
432 Figure amended
[5]
[6]
Clear RE bit in SCR to 0
No
Yes
All data received?
End reception