Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 89 of 910
REJ09B0350-0300
Register Name Abbreviation R/W Initial Value Address
Data Bus
Width
Wake-up sense control register WUESCR R/W H'00 H'FE84 8
Wake-up input interrupt status
register
WUESR R/W H'00 H'FE85 8
Wake-up enable register WER R/W H'00 H'FE86 8
Note: 1. Address in the upper cell: when RELOCATE = 0, address in the lower cell: when
RELOCATE = 1
2. Address in the upper cell: when EIVS = 0, address in the lower cell: when EIVS = 1
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD)
The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence
between interrupt sources and ICRA to ICRD settings is shown in tables 5.2 and 5.3.
Bit Bit Name Initial Value R/W Description
7 to 0 ICRn7 to ICRn0 All 0 R/W Interrupt Control Level
0: Corresponding interrupt source is interrupt
control level 0 (no priority)
1: Corresponding interrupt source is interrupt
control level 1 (priority)
Note: n: A to D