Datasheet

Rev. 3.00 Sep. 28, 2009 Page xi of xliv
REJ09B0350-0300
Item Page Revision (See Manual for Details)
8.4.2 Pulse Division Mode
Figure 8.8 Example of Additional
Pulse Timing (Upper 4 Bits in
PWMREG = B'1000)
215 Figure amended
No pulse added
Pulse added
Resolution width
Additional pulse
Figure 8.9 Example of WMU
Setting
216 Figure amended
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
: Position of additional pulse
1 conversion period
A duty cycle of 0/256 to 255/256 is output as a low-ripple waveform by combining basic pulses and additional pulses.
Duty cycle
Basic
waveform
Additional
pulses
127/256
128/256
129/256
130/256
PWMREG
setting
example
H'7F
H'80
H'81
H'82
112 pulses
128 pulses
128 pulses
128 pulses
15 pulses
0 pulse
1 pulse
2 pulses
10.3.3 Timer I/O Control Register
(TIOR)
Table 10.13 TIORL_0 (channel
0)
253 Table amended
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function TIOCA0 Pin Function
Description
11.3.6 TCM Status Register
(TCMCSR)
312 Table amended
Bit Bit Name R/W Description
0 ⎯ R/W0 Reserved
The initial value should not be changed.
Initial
Value
13.3 Register Descriptions
Table 13.2 Register
Configuration
359 Table amended
Channel Register Name Abbreviation
Initial
ValueR/W Address
Data
Bus
Width
Channel Y Timer control/status register_Y TCSR_Y H'00R/W H'FFF1
H'FEC9*
8