Datasheet

Section 4 Exception Handling

Rev. 3.00 Sep. 28, 2009 Page 80 of 910

REJ09B0350-0300

Figure 4.1 shows an example of the reset sequence.

RES

Internal address bus

Internal read signal

Internal write signal

Internal data bus

Vector

fetch

(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002

(2) Start address (contents of reset exception handling vector address)

(3) Start address ((3) = (2)U + (2)L)

(4) First program instruction

(1) U

(3)

High

Internal

processing

Prefetch of first

program instruction

(2) (2) (4)

(1) L

Figure 4.1 Reset Sequence (Mode 2)

4.3.2 Interrupts Immediately after Reset

If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized,

the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all

interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction

of a program is always executed immediately after a reset, make sure that this instruction

initializes the SP (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Modules after Reset is Cancelled

After a reset is cancelled, the module stop control registers (MSTPCRH, MSTPCRL, MSTPCRA,

MSTPCRB) are initialized, and all modules except the DTC operate in module stop mode.

Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read

from and write to these registers, clear module stop mode. For details on module stop mode, see

section 24, Power-Down Modes.