Datasheet

Section 4 Exception Handling
Rev. 3.00 Sep. 28, 2009 Page 79 of 910
REJ09B0350-0300
Vector Addresses
Exception Source
Vector
Number
Normal Mode
Internal interrupt* 34
⎜
55
H'000088 to H'00008B
⎜
H'0000DC to H'0000DF
External interrupt IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
56
57
58
59
60
61
62
63
H'0000E0 to H'0000E3
H'0000E4 to H'0000E7
H'0000E8 to H'0000EB
H'0000EC to H'0000EF
H'0000F0 to H'0000F3
H'0000F4 to H'0000F7
H'0000F8 to H'0000FB
H'0000FC to H'0000FF
Internal interrupt* 64
⎜
127
H'000100 to H'000103
⎜
H'0001FC to H'0001FF
Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception
Handling Vector Tables.
4.3 Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20
ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A
reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The
chip can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog
Timer (WDT).
4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
and the I bit in CCR is set to 1.
2. The reset exception handling vector address is read and transferred to the PC, and then
program execution starts from the address indicated by the PC.