Datasheet

Section 4 Exception Handling
Rev. 3.00 Sep. 28, 2009 Page 76 of 910
REJ09B0350-0300
4.2 Exception Sources and Exception Vector Table
Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the
exception sources and their vector addresses. The EIVS bit in the system control register 3
(SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended
vector mode.
Table 4.2 Exception Handling Vector Table
(H8S/2140B Group Compatible Vector Mode)
Vector Addresses
Exception Source
Vector
Number Advanced Mode
Reset 0 H'000000 to H'000003
Reserved for system use 1
⎜
3
H'000004 to H'000007
|
H'00000C to H'00000F
Illegal instruction 4 H'000010 to H'000013
Reserved for system use 5 H'000014 to H'000017
Direct transition 6 H'000018 to H'00001B
External interrupt (NMI) 7 H'00001C to H'00001F
Trap instruction (four sources) 8
9
10
11
H'000020 to H'000023
H'000024 to H'000027
H'000028 to H'00002B
H'00002C to H'00002F
Reserved for system use 12
⎜
15
H'000030 to H'000033
|
H'00003C to H'00003F
External interrupt IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6,
KIN7 to KIN0
IRQ7,
KIN15 to KIN8
16
17
18
19
20
21
22
23
H'000040 to H'000043
H'000044 to H'000047
H'000048 to H'00004B
H'00004C to H'00004F
H'000050 to H'000053
H'000054 to H'000057
H'000058 to H'00005B
H'00005C to H'00005F