Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Mar 17, 2006 page 899 of 926
REJ09B0283-0300
T1
φ
A23 to A0
CS7 to CS0
AS
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
DACK0, DACK1
EDACK0 to EDACK3
T2
Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing:
Two-State Access