Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Mar 17, 2006 page 891 of 926
REJ09B0283-0300
Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3
φ
A23 to A0
RAS5 to RAS0
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
t
RCH
t
RCS2
t
AC8
t
CPW2
D15 to D0
AS
Read
Write
DACK and EDACK timing: when DDS = 1 and EDDS = 1
RAS timing: when RAST = 1
Notes:
DACK0, DACK1
EDACK0 to EDACK3
Figure 24.19 DRAM Access Timing: Three-State Burst Access