Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Mar 17, 2006 page 888 of 926
REJ09B0283-0300
Tp
φ
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
Tr Tc1
t
CPW1
t
AC3
t
RCH
t
RCS1
Tc2 Tc1 Tc2
Read
Write
DACK and EDACK timing: when DDS = 1 and EDDS = 1
RAS timing: when RAST = 0
Notes:
DACK0, DACK1
EDACK0 to EDACK3
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
Figure 24.16 DRAM Access Timing: Two-State Burst Access