Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Mar 17, 2006 page 886 of 926
REJ09B0283-0300
Tp
t
AD
t
AS3
t
AH1
t
CSD2
t
PCH2
t
AS2
t
AC1
t
OED1
t
OED1
t
AA3
t
AC4
t
WCS1
t
WCH1
t
WRD2
t
WDD
t
WDS1
t
WDH2
t
RDS2
t
RDH2
t
AH2
t
CSD3
t
CASD1
t
CASD1
t
CASW1
t
AD
φ
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
Tr Tc1 Tc2
Read
Write
DACK0, DACK1
EDACK0 to EDACK3
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
Notes:
DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
t
WRD2
Figure 24.14 DRAM Access Timing: Two-State Access