Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Mar 17, 2006 page 883 of 926
REJ09B0283-0300
Th
t
AD
t
CSD1
t
AS1
t
ASD
t
AS3
t
RSD1
t
RSD1
t
ASD
t
AH1
t
AH3
t
AH2
t
AH3
t
WDH3
t
WSW2
t
WDS3
t
AS4
t
AS3
t
RSD1
t
WRD2
t
WRD1
t
AC4
t
RDH2
t
RSD2
t
AC6
t
RDH1
T1 T2 T3 Tt
φ
A23 to A0
CS7 to CS0
AS
RD
D15 to D0
RD
D15 to D0
D15 to D0
HWR, LWR
Read
(RDNn = 1)
Read
(RDNn = 0)
Write
DACK0, DACK1
EDACK0 to EDACK3
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
t
RDS2
t
WDD
t
RDS1
Figure 24.11 Basic Bus Timing: Three-State Access
(CS
CSCS
CS Assertion Period Extended)