Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Mar 17, 2006 page 871 of 926
REJ09B0283-0300
Clock Timing
Table 24.5 Clock Timing
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 8 MHz to 33 MHz, T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
Clock cycle time t
cyc
30.3 500 ns Figure 24.2
Clock pulse high width t
CH
10 — ns Figure 24.2
Clock pulse low width t
CL
10 — ns
Clock rise time t
Cr
— 5ns
Clock fall time t
Cf
— 5ns
Reset oscillation stabilization time
(crystal)
t
OSC1
10 — ms Figure 24.4 (1)
Software standby oscillation
stabilization time (crystal)
t
OSC2
10 — ms Figure 24.4 (2)
External clock output delay
stabilization time
t
DEXT
500 — µs Figure 24.4 (1)
Clock phase difference
*
t
cdif
1/4 × t
cyc
– 31/4 × t
cyc
+ 3 ns Figure 24.3
Clock pulse high width (SDRAMφ)
*
t
SDCH
10 — ns Figure 24.3
Clock pulse low width (SDRAMφ)
*
t
SDCL
10 — ns Figure 24.3
Clock rise time (SDRAMφ)
*
t
sdcr
— 5 ns Figure 24.3
Clock fall time (SDRAMφ)
*
t
sdcf
— 5 ns Figure 24.3
Note: * Not supported in the H8S/2678 Group.
t
cyc
φ
t
CH
t
Cf
t
CL
t
Cr
Figure 24.2 System Clock Timing