Datasheet

Rev. 3.00 Mar 17, 2006 page vii of l
Main Revisions in This Edition
Item Page Revision (See Manual for Details)
All — All references to Hitachi, Hitachi, Ltd., Hitachi
Semiconductors, and other Hitachi brand names changed to
Renesas Technology Corp. Designation for categories
changed from “series” to “group”
6.2 Input/Output Pins
Table 6.1 Pin
Configuration
124 Symbols amended
Upper column address strobe/upper data mask enable
(Before) UCAS/DQMU → (After) UCAS/DQMU
Lower column address strobe/upper data mask enable
(Before) LCAS/
DQML → (After) LCAS/DQML
124 I/O description amended
Data Transfer acknowledge 0 (DMAC) (Before)
DACK0 →
(After)
Output
7.5.1 Transfer
Modes
Table 7.4 DMAC
Transfer Modes
288 Table 7.4 amended
Transfer Mode Transfer Source Remarks
Short
address
mode
Dual address mode
(1) Sequential mode
• Memory address incremented or
decremented by 1 or 2
• Number of transfers:
1 to 65,536
(2) Idle mode
• Memory address fixed
• Number of transfers:
1 to 65,536
(3) Repeat mode
• Memory address incremented or
decremented by 1 or 2
• Continues transfer after sending
number of transfers (1 to 256) and
restoring the initial value
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmission complete
interrupt
• SCI reception complete
interrupt
• A/D converter conversion
end interrupt
• External request
• Up to 4 channels can
operate independently
• External request
applies to channel B
only
•
Single address mode
applies to channel B
only
289
Transfer Mode Transfer Source Remarks
Full
address
mode
Normal mode
(1) Auto-request
• Transfer request is internally held
• Number of transfers (1 to 65,536) is
continuously sent
• Burst/cycle steal transfer can be
selected
Auto-request
• Max. 2-channel
operation, combining
channels A and B
Section 10 I/O Ports
Table 10.1 Port
Functions
428 to
432
Notes amended
Modes 3
*
1
, 7
CKE
*
2
DQML
*
2
DQMU
*
2
CAS
*
2
RAS
*
2
SDRAMφ
*
2
WE
*
2
432 Notes: 1. Mode 3 is not supported in H8S/2378 Group.
2. These pins are not supported in H8S/2678 Group.