Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Mar 17, 2006 page 831 of 926
REJ09B0283-0300
22.2.6 All-Module-Clocks-Stop Mode
When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip
peripheral functions controlled by MSTPCR (MSTPCR = H'FFFF), or for all the on-chip
peripheral functions except the 8-bit timer (MSTPCR = H'FFFE), executing a SLEEP instruction
while the SSBY bit in SBYCR is cleared to 0 will cause all the on-chip peripheral functions
(except the 8-bit timer and watchdog timer), the bus controller, and the I/O ports to stop operating,
and a transition to be made to all-module-clocks-stop mode, at the end of the bus cycle.
Operation or halting of the 8-bit timer can be selected by means of the MSTP0 bit.
All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15 pins), RES
pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal
program execution state via the exception handling state. All-module-clocks-stop mode is not
cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
22.3 φ
φφ
φ Clock Output Control
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 22.3 shows the state of the φ pin in each processing state.
Table 22.3 φ
φφ
φ Pin State in Each Processing State
Register Setting
DDR PSTOP
Normal
operating state Sleep mode
Software
standby mode
Hardware
standby mode
All-module-
clocks-stop mode
0 X High impedance High impedance High impedance High impedance High impedance
10 φ output φ output Fixed high High impedance φ output
1 1 Fixed high Fixed high Fixed high High impedance Fixed high