Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Mar 17, 2006 page 830 of 926
REJ09B0283-0300
subsequently driven high, a transition is made to the program execution state via the reset
exception handling state.
Hardware Standby Mode Timing: Figure 22.3 shows an example of hardware standby mode
timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 22.3 Hardware Standby Mode Timing
22.2.5 Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI are retained.
After reset clearance, all modules other than the EXDMAC, DMAC, and DTC are in module stop
mode.
The module registers which are set in module stop mode cannot be read or written to.