Datasheet

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 828 of 926

REJ09B0283-0300

Table 22.2 Oscillation Stabilization Time Settings

φφ

[MHz]

STS3 STS2 STS1 STS0

Standby

Time 33 25 20 13 10 8 Unit

0000Reserved——————µs

1 Reserved ——————

1 0 Reserved ——————

1 Reserved ——————

1 0 0 Reserved ——————

1 64 1.9 2.6 3.2 4.9 6.4 8.0

1 0 512 15.5 20.5 25.6 39.4 51.2 64.0

1 1024 31.0 41.0 51.2 78.8 102.4 128.0

1 0 0 0 2048 62.1 81.9 102.4 157.5 204.8 256.0

1 4096 0.12 0.16 0.20 0.32 0.41 0.51 ms

1 0 16384 0.50 0.66 0.82 1.26 1.64 2.05

1 32765 0.99 1.31 1.64 2.52 3.28 4.10

1 0 0 65536 1.99 2.62 3.28 5.04 6.55 8.19

1 131072 3.97 5.24 6.55 10.08 13.11 16.38

1 0 262144 7.94 10.49 13.11 20.16 26.21 32.77

1 524288 15.89 20.97 26.21 40.33 52.43 65.54

: Recommended time setting

Note: * φ is the frequency divider output.

Software Standby Mode Application Example: Figure 22.2 shows an example in which a

transition is made to software standby mode at the falling edge on the NMI pin, and software

standby mode is cleared at the rising edge on the NMI pin.

In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.