Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Mar 17, 2006 page 827 of 926
REJ09B0283-0300
IRQ15 is generated. Software standby mode cannot be cleared if the interrupt has been masked
on the CPU side or has been designated as a DTC activation source.
• Clearing with the RES Pin
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
• Clearing with the STBY Pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to
STS0 in SBYCR should be set as described below.
• Using a Crystal Oscillator
Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time.
Table 22.2 shows the standby times for operating frequencies and settings of bits STS3 to
STS0.
• Using an External Clock
A PLL circuit stabilization time is necessary. Refer to table 22.2 to set the wait time.