Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Mar 17, 2006 page 826 of 926
REJ09B0283-0300
22.2.2 Sleep Mode
Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in
SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of
the CPU’s internal registers are retained. Other peripheral functions do not stop.
Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
• Exiting Sleep Mode by Interrupts
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exiting Sleep Mode by RES Pin
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high starts the CPU performing reset exception processing.
• Exiting Sleep Mode by STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
22.2.3 Software Standby Mode
Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in
SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral
functions, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM
data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O
ports, are retained. Whether the address bus and bus control signals are placed in the high-
impedance state or retain the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by an external interrupt
(NMI pin, or pins IRQ0 to IRQ15), or by means of the RES pin or STBY pin. Setting the SSI bit
in SSIER to 1 enables IRQ0 to IRQ15 to be used as software standby mode clearing sources.
• Clearing with an Interrupt
When an NMI or IRQ0 to IRQ15 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to
the entire LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ15 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to