Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Mar 17, 2006 page 825 of 926
REJ09B0283-0300
MSTPCRL
Bit Bit Name Initial Value R/W Module
7 MSTP7 1 R/W —
6 MSTP6 1 R/W A/D converter
5 MSTP5 1 R/W —
4 MSTP4 1 R/W —
3 MSTP3 1 R/W Serial communication interface 2 (SCI_2)
2 MSTP2 1 R/W Serial communication interface 1 (SCI_1)
1 MSTP1 1 R/W Serial communication interface 0 (SCI_0)
0 MSTP0 1 R/W 8-bit timer (TMR)
22.2 Operation
22.2.1 Clock Division Mode
When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to
clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and
on-chip peripheral functions all operate on the operating clock (1/2, 1/4, 1/8, 1/16, or 1/32)
specified by bits SCK2 to SCK0.
Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode at the end of the bus cycle, and clock division mode is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external interrupt, clock
division mode is restored.
When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.