Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Mar 17, 2006 page 821 of 926
REJ09B0283-0300
Program-halted stateProgram execution state
High-speel mode
(Internal clock is PLL
circuit output clock)
Reset state
STBY pin = low
STBY pin = high
RES pin = low
SSBY = 0
MSTPCR =
H'FFFF (H'FFFE),
SSBY = 0
SSBY = 1
SCK2 to
SCK0 ≠ 0
RES pin = high
SCK2 to
SCK0 = 0
SLEEP
instruction
Interrupt
*
1
: Transition after exception handling : Power- down mode
SLEEP
instruction
Any interrupt
SLEEP
instruction
External
interrupt
*
2
Notes: When a transition is made between modes by means of an interrupt, the transition cannot
be made on interrupt source generation alone. Ensure that interrupt handling is performed
after accepting the interrupt request.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
From any state except hardware standby mode, a transition to the reset state occurs when
RES is driven low.
1. NMI, IRQ0 to IRQ15, 8-bit timer interrupts, watchdog timer interrupts.
(8-bit timer interrupts are valid when MSTP0 = 0.)
2. NMI, IRQ0 to IRQ15
(IRQ0 to IRQ15 are valid when the corresponding bit in SSIER is 1.)
Hardware
standby mode
Sleep mode
All
module-clocks-stop
mode
Software
standby mode
Clock division
mode
Figure 22.1 Mode Transitions