Datasheet

Section 21 Clock Pulse Generator
Rev. 3.00 Mar 17, 2006 page 816 of 926
REJ09B0283-0300
Table 21.3 External Clock Input Conditions
V
CC
= 3.0 V to 3.6 V
Item Symbol Min Max Unit Test Conditions
External clock input
low pulse width
t
EXL
15 — ns Figure 21.5
External clock input
high pulse width
t
EXH
15 — ns
External clock rise time t
EXr
— 5ns
External clock fall time t
EXf
— 5ns
Clock low pulse width t
CL
0.4 0.6 t
cyc
Clock high pulse width t
CH
0.4 0.6 t
cyc
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 21.5 External Clock Input Timing
21.3 PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC1 and the STC0 bits in PLLCR.
The phase of the rising edge of the internal clock is controlled so as to match that of the rising
edge of the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes valid after a transition to software standby mode. The
transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR.
For details on SBYCR, refer to section 22.1.1, Standby Control Register (SBYCR).
1. The initial PLL circuit multiplication factor is 1.