Datasheet

Section 21 Clock Pulse Generator
Rev. 3.00 Mar 17, 2006 page 813 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 2 to 0
Select the division ratio.
000: 1/1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
101: 1/32
11X: Setting prohibited
Legend: X: Don’t care
21.1.2 PLL Control Register (PLLCR)
PLLCR sets the frequency multiplication factor used by the PLL circuit.
Bit Bit Name Initial Value R/W Description
7
to
4
— All 0 — Reserved
These bits are always read as 0 and cannot be
modified.
3— 0 R/WReserved
This bit can be read from or written to. However,
the write value should always be 0.
2— 0 R/WReserved
This bit is always read as 0 and cannot be
modified.
1
0
STC1
STC0
0
0
R/W
R/W
Frequency Multiplication Factor
The STC bits specify the frequency multiplication
factor used by the PLL circuit.
00: × 1
01: × 2
10: × 4
11: Setting prohibited