Datasheet

Section 20 Masked ROM

Rev. 3.00 Mar 17, 2006 page 810 of 926

REJ09B0283-0300

H'000000

H'000002

H'00FFFE

H'000001

H'000003

H'00FFFF

Internal data bus (upper 8 bits)

Modes 4 and 7 Modes 5 and 6

Internal data bus (lower 8 bits)

H'100000

H'100002

H'10FFFE

H'100001

H'100003

H'10FFFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 20.3 Block Diagram of 64-kbyte Masked ROM (HD6432673)

The operating mode enables or disables the on-chip ROM. The operating mode is selected by the

mode setting pins, such as the FWE and MD2 to MD0 pins as shown in table 3.1. Select modes 4

to 7 when the on-chip ROM is used, and mode 1 or 2 when the on-chip ROM is not used. The on-

chip ROM is allocated in area 0.