Datasheet

Section 19 Flash Memory (F-ZTAT Version)
Rev. 3.00 Mar 17, 2006 page 797 of 926
REJ09B0283-0300
Start
End of programming
End sub
Set SWE bit in FLMCR1
Wait (x) ms
n = 1
m = 0
Sub-routine-call
Sub-routine-call
See note 7 for pulse width
Note 7: Write Pulse Width
Start of programming
Write pulse application
Set PSU bit in FLMCR1
Enable WDT
Set P bit in FLMCR1
Wait (y) µs
Clear P bit in FLMCR1
Wait (z1) ms or (z2) ms or (z3) ms
Clear PSU bit in FLMCR1
Wait (α) ms
Disable WDT
Wait (β) ms
Write pulse application subroutine
NG
NG
NG
NG
NG NG
OK
OK
OK
OK
OK
Wait (γ) ms
Wait (ε) ms
*2
*4
*6
*6
*6
*6
*6 *6
*6
*5 *6
*6
*6
*6
*1
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Additional program data computation
Transfer additional program data to
additional program data area
Write data = verify
data?
*4
*1
*4
*3
Reprogram data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
128-byte
data verification
completed?
m = 0?
6 ≥ n ?
6 ≥ n ?
Increment address
Programming failure
OK
Clear SWE bit in FLMCR1
n ≥ (N)?
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Write pulse application
(z1) µs or (z2) µs
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional program data
storage area (128 bytes)
Store 128-byte program data in program
data area and reprogram data area
Number of Writes (n)
1
2
3
4
5
6
7
8
9
10
11
12
13
.
.
.
998
999
1000
Write Time (z) ms
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
.
.
.
z2
z2
z2
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address
written to must be H'00 or H'80. A 128-byte data transfer must be performed even
if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra
addresses.
2. Verify data is read in 16-bit (W) units.
3. The reprogram data is given by the operation of the following tables (comparison
between stored data in the program data area and verify data). Programming is
executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for
which programming has been completed will be subjected to additional
programming if they fail the subsequent verify operation.
4. A 128-byte areas for storing program data, reprogram data, and additional
program data must be provided in the RAM. The contents of the reprogram and
additional program data are modified as programming proceeds.
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of the
programming operation. See note 7 for the pulse widths. When writing of
additional-programming data is executed, a (z3) µs write pulse should be applied.
Reprogram data X' means reprogram data when the write pulse is applied.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 24.6, Flash
Memory Characteristics.
0
1
0
1
0
1
1
0
1
Comments
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Program Data Operation Chart
Transfer reprogram data to reprogram
data area
n ← n + 1
Note: Use a z3 µs write pulse for additional programming.
Sequentially write 128-byte data in
additional program data area in RAM to
flash memory
Write pulse application
(z3) µs
(additional programming)
Wait (θ) ms
Wait (η) ms
Wait (θ) ms
Original Data
(D)
Verify Data
(V)
Reprogram Data
(X)
0
1
0
1
0
1
0
1
Comments
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
Additional Program Data Operation Chart
Reprogram Data
(X')
Verify Data
(V)
Additional Program
Data (Y)
Figure 19.10 Program/Program-Verify Flowchart