Datasheet

Section 16 A/D Converter
Rev. 3.00 Mar 17, 2006 page 754 of 926
REJ09B0283-0300
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
Legend:
(1) : ADCSR write cycle
(2) : ADCSR address
t
D
: A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 16.2 A/D Conversion Timing
Table 16.3 A/D Conversion Time (Single Mode)
• H8S/2678 Group
CKS1 = 0 CKS1 = 1
CKS = 0 CKS = 1 CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max
A/D conversion
start delay time
t
D
18 — 33 4 — 510— 17 6 — 9
Input sampling
time
t
SPL
— 127 ——15 ——63 ——31 —
A/D conversion
time
t
CONV
515 — 530 67 — 68 259 — 266 131 — 134
Note: Values in the table are the number of states.