Datasheet

Section 16 A/D Converter
Rev. 3.00 Mar 17, 2006 page 748 of 926
REJ09B0283-0300
• H8S/2678R Group
Bit Bit Name Initial Value R/W Description
7ADF 0 R/(W)
*
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC or DMAC is activated by an
ADI interrupt and ADDR is read
6 ADIE 0 R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request
enabled when 1 is set
5 ADST 0 R/W A/D Start
Clearing this bit to 0 stops A/D conversion, and
the A/D converter enters wait state.
Setting this bit to 1 starts an A/D conversion. In
single mode, cleared to 0 automatically when
conversion on the specified channel ends. In scan
mode, conversion continues sequentially on the
specified channels until this bit is cleared to 0 by
software, a reset, or a transition to software
standby mode, hardware standby mode or module
stop mode.
4— 0 — Reserved
This bit is always read as 0 and cannot be
modified.