Datasheet

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 744 of 926

REJ09B0283-0300

16.3 Register Descriptions

The A/D converter has the following registers.

• A/D data register A (ADDRA)

• A/D data register B (ADDRB)

• A/D data register C (ADDRC)

• A/D data register D (ADDRD)

• A/D data register E (ADDRE)

• A/D data register F (ADDRF)

• A/D data register G (ADDRG)

• A/D data register H (ADDRH)

• A/D control/status register (ADCSR)

• A/D control register (ADCR)

16.3.1 A/D Data Registers A to H (ADDRA to ADDRH)

There are four 16-bit read-only ADDR registers, ADDRA to ADDRD (H8S/2678 Group) and

eight 16-bit read-only ADDR registers, ADDRA to ADDRH (H8S/2678R Group), used to store

the results of A/D conversion. The ADDR registers, which store a conversion result for each

channel, are shown in table 16.2.

The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. ADDR

must not be accessed in 8-bit units and must be accessed in 16-bit units.

In the H8S/2678 Group, the data bus between the CPU and the A/D converter is 8-bit width. The

upper byte can be read directly from the CPU, but the lower byte should be read via a temporary

is read. When reading the ADDR, read the only upper byte, or read in word unit.

In the H8S/2678R Group, the data bus between the CPU and the A/D converter is 16-bit width.

The data can be read directly from the CPU.