Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 3.00 Mar 17, 2006 page 724 of 926
REJ09B0283-0300
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds
D0 D1 D2 D3 D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
TDRE
TEND
[6]
FER/ERS
Transfer to TSR from TDR Transfer to TSR from TDR
Transfer to TSR
from TDR
[7] [9]
[8]
Figure 15.26 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
generation timing is shown in figure 15.27.
Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data
12.5etu
TXI
(TEND interrupt)
11.0etu
DE
Guard
time
When GM = 0
When GM = 1
: Start bit
: Data bits
: Parity bit
: Error signal
Legend:
Ds
D0 to D7
Dp
DE
Figure 15.27 TEND Flag Generation Timing in Transmission Operation