Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 3.00 Mar 17, 2006 page 721 of 926
REJ09B0283-0300
falling edge of the start bit using the basic clock, and performs internal synchronization. As shown
in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th
pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given
by the following formula.
M = (0.5 – ) – (L – 0.5) F – (1 + F) × 100 [%]
1
2N

D – 0.5

N
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Internal
basic clock
372 clocks
186 clocks
Receive data
(RxD)
Synchronization
sampling timing
D0 D1
Data sampling
timing
185
371 0
371
185
0
0
Start bit
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Bit Rate)