Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 3.00 Mar 17, 2006 page 679 of 926
REJ09B0283-0300
15.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode Bit Rate Error
Asynchronous
Mode
B =
64 × 2
2n – 1
× (N + 1)
φ × 10
6
B × 64 × 2
2n – 1
× (N + 1)
φ × 10
6
Error (%) =
{}
– 1 × 100
Clocked
Synchronous
Mode
B =
Smart Card
Interface Mode
B =
Error (%) =
B × S × 2
2n + 1
× (N + 1)
φ × 10
6
{}
– 1 × 100
8 × 2
2n – 1
× (N + 1)
φ × 10
6
S × 2
2n + 1
× (N + 1)
φ × 10
6
Note: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting SMR Setting
CKS1 CKS0 n BCP1 BCP0 S
000 0032
011 0164
102 10372
113 11256