Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 3.00 Mar 17, 2006 page 673 of 926
REJ09B0283-0300
15.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ in normal serial communication interface mode and Smart Card interface
mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name Initial Value R/W Description
7 TDRE 1 R/(W)
*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE
= 1
• When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
6 RDRF 0 R/(W)
*
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading
RDRF = 1
• When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared
to 0.