Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 3.00 Mar 17, 2006 page 669 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
4O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on setting this bit in Smart Card
interface mode, refer to section 15.7.2, Data
Format (Except for Block Transfer Mode).
3
2
BCP1
BCP0
0
0
R/W
R/W
Basic Clock Pulse 1 and 0
These bits select the number of basic clock
periods in a 1-bit transfer interval on the Smart
Card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, refer to section 15.7.4, Receive Data
Sampling Timing and Reception Margin. S stands
for the value of S in BRR (see section 15.3.9, Bit
Rate Register (BRR)).
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 1 and 0
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 15.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 15.3.9, Bit Rate
Register (BRR)).