Datasheet

Section 14 Watchdog Timer
Rev. 3.00 Mar 17, 2006 page 659 of 926
REJ09B0283-0300
14.6.5 Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
14.6.6 System Reset by WDTOVF
WDTOVFWDTOVF
WDTOVF Signal
If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly.
Make sure that the WDTOVF signal is not input logically to the RES pin.
To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 14.6.
Reset input
Reset signal to entire system
This LSI
RES
WDTOVF
Figure 14.6 Circuit for System Reset by WDTOVF
WDTOVFWDTOVF
WDTOVF Signal (Example)