Datasheet

Section 14 Watchdog Timer
Rev. 3.00 Mar 17, 2006 page 650 of 926
REJ09B0283-0300
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal
*
WDTOVF
Reset
control
RSTCSR TCNT TSCR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Internal clock
sources
Bus
interface
Module bus
TCSR
TCNT
RSTCSR
Note: * An internal reset signal can be generated by the register setting.
: Timer control/status register
: Timer counter
: Reset control/status register
WDT
Legend:
Internal bus
Figure 14.1 Block Diagram of WDT
14.2 Input/Output Pin
Table 14.1 shows the WDT pin configuration.
Table 14.1 Pin configuration
Name Symbol I/O Function
Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog
timer mode
14.3 Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, refer to
section 14.6.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)