Datasheet

Section 13 8-Bit Timers (TMR)
Rev. 3.00 Mar 17, 2006 page 644 of 926
REJ09B0283-0300
13.8.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 13.11 shows this operation.
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
NM
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 13.11 Contention between TCNT Write and Increment