Datasheet

Section 1 Overview
Rev. 3.00 Mar 17, 2006 page 17 of 926
REJ09B0283-0300
Pin No.
Type Symbol
FP-144G
(H8S/2678
Group)
FP-144H
(H8S/2678R
Group)
I/O Function
DMA controller
(DMAC)
TEND1
TEND0
(TEND1)
(TEND0)
82, 81,
40, 36
82, 81,
40, 36
Output These signals indicate the end of
DMAC data transfer.
The input pins of TENDn and
(TENDn) are selected by the port
function control register 2 (PFCR2)
of port 3. (n = 1, 0)
DACK1
DACK0
(DACK1)
(DACK0)
84, 83,
42, 41
84, 83,
42, 41
Output DMAC single address transfer
acknowledge signals.
The input pins of DACKn and
(DACKn) are selected by the port
function control register 2 (PFCR2)
of port 3. (n = 1, 0)
EXDMA
controller
(EXDMAC)
EDREQ3
to
EDREQ0
141, 140,
35, 34
141, 140,
35, 34
Input These signals request EXDMAC
activation.
ETEND3
to
ETEND0
2, 142,
40, 36
2, 142,
40, 36
Output These signals indicate the end of
EXDMAC data transfer.
EDACK3
to
EDACK0
4, 3, 42,
41
4, 3, 42,
41
Output EXDMAC single address transfer
acknowledge signals.
EDRAK3
to
EDRAK0
51, 50,
59, 58
51, 50,
59, 58
Output These signals notify an external
device of acceptance and start of
execution of a DMA transfer
request.
16-bit timer
pulse unit
(TPU)
TCLKA
TCLKB
TCLKC
TCLKD
45, 46,
49, 51
45, 46,
49, 51
Input External clock input pins.
TIOCA0
TIOCB0
TIOCC0
TIOCD0
43, 44,
45, 46
43, 44,
45, 46
Input/
output
TGRA_0 to TGRD_0 input capture
input/output compare output/PWM
output pins.
TIOCA1
TIOCB1
48, 49 48, 49 Input/
output
TGRA_1 and TGRB_1 input capture
input/output compare output/PWM
output pins.