Datasheet

Section 13 8-Bit Timers (TMR)
Rev. 3.00 Mar 17, 2006 page 632 of 926
REJ09B0283-0300
Table 13.2 Clock Input to TCNT and Count Condition
TCR
Channel Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0 Description
TMR_0 0 0 0 Clock input disabled
1 Internal clock, counted at falling edge of φ/8
1 0 Internal clock, counted at falling edge of φ/64
1 Internal clock, counted at falling edge of φ/8192
1 0 0 Count at TCNT_1 overflow signal
*
TMR_1 0 0 0 Clock input disabled
1 Internal clock, counted at falling edge of φ/8
1 0 Internal clock, counted at falling edge of φ/64
1 Internal clock, counted at falling edge of φ/8192
1 0 0 Count at TCNT_0 compare match A
*
All 1 0 1 External clock, counted at rising edge
1 0 External clock, counted at falling edge
1 1 External clock, counted at both rising and falling edges
Note: * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.