Datasheet

Section 1 Overview
Rev. 3.00 Mar 17, 2006 page 16 of 926
REJ09B0283-0300
Pin No.
Type Symbol
FP-144G
(H8S/2678
Group)
FP-144H
(H8S/2678R
Group)
I/O Function
Bus control CAS — 104 Output Column address strobe signal for
the synchronous DRAM of the
synchronous DRAM interface.
WE — 105 Output Write enable signal for the
synchronous DRAM of the
synchronous DRAM interface.
WAIT 85 85 Input Requests insertion of a wait state in
the bus cycle when accessing
external 3-state address space.
OE
(OE)
112, 133 112, 133 Output Output enable signal for DRAM
interface space.
The output pins of OE and (OE) are
selected by the port function control
register 2 (PFCR2) of port 3.
CKE
(CKE)
— 112, 133 Output Clock enable signal of the
synchronous DRAM interface
space.
The output pins of CKE and (CKE)
are selected by the port function
control register 2 (PFCR2) of port 3.
Interrupt
signals
NMI 38 38 Input Nonmaskable interrupt request pin.
Fix high when not used.
IRQ15 to
IRQ0
87, 86,
84 to 81,
61, 60,
130 to 127,
110 to 107
87, 86,
84 to 81,
61, 60,
130 to 127,
110 to 107
(IRQ15)
to (IRQ0)
59 to 52,
112, 111,
4 to 2,
142 to 140
59 to 52,
112, 111,
4 to 2,
142 to 140
Input These pins request a maskable
interrupt.
The input pins of DREQn and
(DREQn) are selected by the IRQ
pin select register (ITSR) of the
interrupt controller. (n = 0 to 15)
DMA controller
(DMAC)
DREQ1
DREQ0
(DREQ1)
(DREQ0)
61, 60,
35, 34
61, 60,
35, 34
Input These signals request DMAC
activation.
The input pins of DREQn and
(DREQn) are selected by the IRQ
pin select register (ITSR) of the
interrupt controller. (n = 0 to 15)