Datasheet

Section 12 Programmable Pulse Generator (PPG)
Rev. 3.00 Mar 17, 2006 page 615 of 926
REJ09B0283-0300
12.4 Operation
Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
Output trigger signal
Pulse output pin
Internal data bus
Normal output/inverted output
C
PODRQD
NDER
Q
NDRQD
DDR
Figure 12.2 Overview Diagram of PPG