Datasheet

Section 12 Programmable Pulse Generator (PPG)
Rev. 3.00 Mar 17, 2006 page 611 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
7
to
4
— All 1 — Reserved
These bits are always read as 1 and cannot be
modified.
3
2
1
0
NDR11
NDR10
NDR9
NDR8
0
0
0
0
R/W
R/W
R/W
R/W
Next Data Register 11 to 8
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit Bit Name Initial Value R/W Description
7
6
5
4
NDR7
NDR6
NDR5
NDR4
0
0
0
0
R/W
R/W
R/W
R/W
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
to
0
— All 1 — Reserved
These bits are always read as 1 and cannot be
modified.