Datasheet

Section 1 Overview
Rev. 3.00 Mar 17, 2006 page 14 of 926
REJ09B0283-0300
Pin No.
Type Symbol
FP-144G
(H8S/2678
Group)
FP-144H
(H8S/2678R
Group)
I/O Function
Operating
mode control
DCTL — 132 Input When this pin is driven high,
SDRAMφ dedicated to the
synchronous DRAM is output.
When not using the synchronous
DRAM interface, drive this pin low.
The level of this pin must not be
changed during operation.
System
control
RES 93 93 Input When this pin is driven low, the chip
is reset.
STBY 100 100 Input When this pin is driven low, a
transition is made to hardware
standby mode.
BREQ 115 115 Input Requests chip to release the bus to
an external bus master.
BREQO 113 113 Output External bus request signal used
when an internal bus master
accesses external space when the
external bus is released.
BACK 114 114 Output Indicates that the bus has been
released to an external bus master.
FWE 62 — Input Enables/disables flash memory.
This pin is only used in the flash
memory version.
Address bus A23 to
A0
32 to 27,
25 to 20,
18 to 13,
11 to 6
32 to 27,
25 to 20,
18 to 13,
11 to 6
Output These pins output an address.
Data bus D15 to
D0
72 to 75,
77 to 80,
63 to 66,
68 to 71
72 to 75,
77 to 80,
63 to 66,
68 to 71
Input/
output
These pins constitute a bidirectional
data bus.
Bus control CS7 to
CS0
112, 111,
106 to 101
112, 111,
106 to 101
Output Signals that select division areas 7
to 0 in the external address space.
AS 91 91 Output When this pin is low, it indicates that
address output on the address bus
is valid.