Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 603 of 926
REJ09B0283-0300
11.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, when
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.53 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
H'FFFF M
TCNT write data
TCFV flag
Prohibited
Figure 11.53 Contention between TCNT Write and Overflow
11.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
11.10.14 Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore
be disabled before entering module stop mode.