Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 601 of 926
REJ09B0283-0300
11.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.51 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T1 T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 11.51 Contention between Buffer Register Write and Input Capture