Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 600 of 926
REJ09B0283-0300
11.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.50 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T1 T2
M
TGR
M
TGR address
Figure 11.50 Contention between TGR Write and Input Capture