Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 598 of 926
REJ09B0283-0300
11.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 11.48 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T1 T2
N
TGR
N M
Buffer register write data
Figure 11.48 Contention between Buffer Register Write and Compare Match