Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 597 of 926
REJ09B0283-0300
11.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 11.47 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T1 T2
N M
TGR write data
TGR
N N + 1
Prohibited
Figure 11.47 Contention between TGR Write and Compare Match